1. Field of the Invention
The present invention relates to a microprogram control system having a microprogram memory which comprises decoding means for decoding addresses of a microprogram and memory means connected with the decoding means through micro instruction selecting lines for storing micro instructions of the microprogram, wherein the execution of a macro instruction read from a main memory is completed by successively executing a set of micro instructions prepared for the macro instruction in the memory means. Particularly, the invention relates to a microprogram control system having a microprogram memory which can be constructed of a reduced quantity of hardware or can utilize its storage capacity effectively, while having compatibility or flexibility for general purpose use, and further which is suited for application of LSI technology.
2. Description of the Related Art
With the recent remarkable progress in the MOS (Metal Oxide Semiconductor) technology, a high density of integration in integrated circuits has been achieved, resulting in the appearance of microcomputers of higher performance and improved functions. The higher density of integration is accompanied by more complicated logic, and thus main concerns and efforts are now concentrated on methods of constructing an integrated circuit by means of logic circuits which have regular structures. As one of them, a microprogram control system is well known.
In such a system, there is usually provided a memory called a microprogram memory or a control memory for its exclusive use which comprises a ROM (Read Only Memory). There are stored in the ROM many micro instruction sets, each of which corresponds to a specific macro instruction. Namely, one of the macro instructions is composed of a plurality of micro instructions which are prepared suitably for execution of the macro instruction. Although many micro instructions for various kinds of macro instructions are stored in the ROM, it is rarely the case that all the micro instructions for completing the execution of a certain macro instruction different from those for some other macro instructions. On the contrary, there are many cases where some micro instructions for a certain macro instruction are common to those for many other macro instructions. In some cases, a micro instruction for one macro instruction has the same function as that for an other macro instruction except the difference in the next address included in both micro instructions. In a conventional system, all the micro instructions have been assigned particular addresses in the address space of the ROM, whether or not the content of the micro instructions is the same as or similar to that of other micro instructions. Consequently, in the ROM, there exist a plurality of micro instructions which have a common bit pattern in an considerable part thereof, so that the ROM is inefficiently used. This results in an increase in the necessary storage capacity of the ROM.
In order to improve on this storage redundancy problem, Japanese Patent Laid-Open No. 57-203141 is known, for example. According thereto, there are provided a first microprogram memory for storing micro instructions having a long word length which are capable of general purpose use, a second microprogram memory for storing micro instructions of a shortened word length which are used often but for a limited purpose and a bit pattern generator which produces a signal having a predetermined bit pattern and adds the produced signal to the shortened word length micro instruction to restore the long word length micro instruction when the shortened word length micro instruction is read out from memory.
In this way, micro instructions used frequently are described and stored shortened word length so as to increase the working efficiency of the capacity of the ROM. Although this system is effective as a means to reduce the capacity of the ROM, it lacks compatibility for general purpose use, since the processing content capable of being expressed by the micro instructions of a shortened word length is limited and not all micro instructions can be expressed, when the ROM storing the micro instructions of the shortened word length is employed for storing other micro instructions. This is because a group of micro instructions of shortened word length for use of the limited purpose is formed therein. Also, when micro instructions for processing macro instructions of a different instruction system are formed, not all the micro instructions can be expressed by the micro instructions already stored in the ROM for those of a shortened word length in which the group of the exclusively-used micro instructions is formed. Consequently, it is necessary to construct other bit pattern generators generating many types of bit patterns as generated by the aforesaid bit patern generator. Thus, the ROM storing the micro instructions of a shortened word length lacks compatibility and flexibility for general purpose use.